Test MP+dmb.sy+addr-ctrl-pos-[fr-rf]-pos

AArch64 MP+dmb.sy+addr-ctrl-pos-[fr-rf]-pos
"DMB.SYdWW Rfe DpAddrdR DpCtrldR PosRR FrLeave RfBack PosRR Fre"
Cycle=Rfe DpAddrdR DpCtrldR PosRR FrLeave RfBack PosRR Fre DMB.SYdWW
Relax=
Safe=Rfe Fre PosRR DMB.SYdWW DpAddrdR DpCtrldR [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe DpAddrdR DpCtrldR PosRR FrLeave RfBack PosRR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X4=z; 1:X6=x;
2:X1=x;
}
 P0          | P1                  | P2          ;
 MOV W0,#2   | LDR W0,[X1]         | MOV W0,#1   ;
 STR W0,[X1] | EOR W2,W0,W0        | STR W0,[X1] ;
 DMB SY      | LDR W3,[X4,W2,SXTW] |             ;
 MOV W2,#1   | CBNZ W3,LC00        |             ;
 STR W2,[X3] | LC00:               |             ;
             | LDR W5,[X6]         |             ;
             | LDR W7,[X6]         |             ;
             | LDR W8,[X6]         |             ;
             | LDR W9,[X6]         |             ;
Observed
    y=1; x=1; 1:X9=2; 1:X8=2; 1:X7=0; 1:X5=2; 1:X0=0;
and y=1; x=2; 1:X9=2; 1:X8=2; 1:X7=0; 1:X5=1; 1:X0=0;
and y=1; x=2; 1:X9=1; 1:X8=1; 1:X7=0; 1:X5=1; 1:X0=0;